Accurately predicting surface topography evolution during semiconductor processing is essential for advanced device manufacturing and Process/Design Technology Co-Optimization (DTCO). DTCO bridges semiconductor process development and circuit design, ensuring that manufacturing constraints, device performance, and power efficiency are optimized together. By integrating insights from process modeling into early design stages, DTCO helps enhance yield, reduce costs, and enable continued scaling of semiconductor devices. Feature-scale modeling plays a central role in this effort, as it connects reactor-scale process conditions, such as ion and neutral fluxes and their distributions, to the resulting material modifications at the nanoscale. In this talk, we present ViennaPS, a flexible and efficient framework for simulating topography evolution during etching and deposition, enabling predictive process design and optimization. To improve model accuracy, ViennaPS incorporates atomistic-scale insights (DFT/MD), which help characterize fundamental surface reactions, such as adsorption, desorption, and sputtering. These reaction mechanisms, in turn, define surface evolution models used in feature-scale simulations. Chamber-scale plasma simulations provide spatially resolved flux distributions of reactive species, ensuring that feature-scale models reflect the local process conditions imposed by reactor design and operating parameters. Beyond physics-based modeling, we explore the automated extraction and optimization of model parameters from SEM/TEM images, where experimental feature profiles guide the refinement of topography models, reaction rates, and material-specific properties. Additionally, equipment-scale surrogate models can be integrated into ViennaPS to incorporate realistic plasma reactor effects while maintaining computational efficiency. This multi-scale approach allows for rapid process tuning and improves the predictive power of semiconductor process simulations. By combining first-principles insights, chamber-scale process inputs, and automated model calibration, ViennaPS provides a powerful and versatile framework for semiconductor topography evolution modeling. We demonstrate its capabilities through case studies, showcasing how this integrated approach improves process control, reduces reliance on empirical fitting, and accelerates technology development.

Dr. Lado Filipovic is an Associate Professor and Director of the Christian Doppler Laboratory for Multi-Scale Process Modeling at TU Wien’s Institute for Microelectronics in Vienna, Austria. He earned his PhD degree in Microelectronics from TU Wien and specializes in semiconductor sensor technology and process simulations. His research focuses on multi-scale process modeling, integrated sensors, and novel semiconductor materials, with an emphasis on equipment-informed inverse design and advanced semiconductor fabrication. Dr. Filipovic leads multiple research projects aimed at enhancing process simulations, improving device performance, and advancing sensor integration. His team has developed open-source TCAD tools, including ViennaPS, which is widely used for process and device modeling. A Senior Member of IEEE, he collaborates with leading industry partners and academic institutions worldwide to advance semiconductor processes, devices, and manufacturing technologies through improved modeling and simulation.