The inherently probabilistic nature of quantum mechanics means that many quantum algorithms must be repeated a large number of times to perform a computation. Such algorithms would benefit from pipelining, where an iteration of the quantum circuit starts for a fresh set of qubits before the operations on the previous set of qubits has finished. This approach changes runtime scaling from multiplicative to additive as functions of circuit depth and number of qubits. Pipelining is used in classical computing, and enabled by physically moving around bits. This requires a much larger number of structures compared to the number of bits.
The silicon spin qubit platform, based on structures similar to microprocessors, is well suited for defining a qubit processor as a large number of structures and moving qubits. To this end, spin carrying electrons may be synchronously shuttled through a large grid, which has recently shown to be a high-fidelity operation [Yoneda et al. 2020], to realise pipelining. To demonstrate feasibility in the selected platform, we lay out protocols for spin qubits to acquire the phases associated with single- and two-qubit operations as they process through the pipeline. We meet the stringent requirements of synchronisation, high fidelities, and challenges associated with qubit frequency variability using small controlled g-factor Stark shifts, new composite two-qubit circuit identities, and a multi-tone transversal drive. The qubit frequency variability is governed by fabrication processes. As such, control protocols working around variability rather than requiring increased homogeneity are expected to be useful.
I studied theoretical physics in the University of Helsinki, where I did my undergrad projects in Prof. Mikko Möttönen's group on theoretical quantum optics and experimental superconducting qubit control. I joined University College London's Quantum Technologies PhD program to do my PhD in Prof. John Morton's group, and worked as a quantum engineer at his startup Quantum Motion Technologies (QMT) in projects related to silicon spin qubits, with particular interest in qubit couplers for scalable architectures.
At this interface, I've worked out the required hardware and qubit control protocols to realise pipelining - a form of classical parallelisation - with silicon spin qubits. I was the main designer for the first generations of QMT's qubit devices, made using imec's 300 mm 3-gate-layer process, with complexity ranging from process control monitors to small 2xN quantum dot (QD) arrays. Using a subset of these devices, I took the first experimental steps towards demonstrating mediated exchange in SiMOS, with estimated high-fidelity operation above MHz. I've also observed electrically driven electron spin singlet-triplet oscillations in a nanowire QD device. Recently I've worked help realise kinetic inductance based parametric amplifiers for spin memory experiments using quadrature readout.
In my spare time, I enjoy bouldering, silly conversations, reading, and sometimes drawing.